US Patent 11769539 Integrated circuit with asymmetric arrangements of memory arrays

An integrated circuit includes multiple memory cells, a first pair of complementary data lines, a second pair of complementary data lines, multiple first word lines, and multiple second word lines. The memory cells include a first array of memory cells and a second array of memory cells. The first pair of complementary data lines are coupled to the first array of memory cells. The second pair of complementary data lines are coupled to the second array of memory cells. Lengths of the first pair of complementary data lines are shorter than lengths of the second pair of complementary data lines. The first word lines and the second word lines are arranged according to a predetermined ratio of a number of the first word lines to a number of the second word lines. The predetermined ratio is less than 1.