Patent attributes
A manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure is disclosed. The method includes forming a peripheral circuitry in a peripheral device region, wherein the peripheral circuitry includes a peripheral transistor at least partially formed in the semiconductor substrate and having a first gate dielectric formed in a first high temperature process step. The method further includes forming a plurality of memory cells in a memory cell region, each of said memory cells including an access transistor at least partially formed in a semiconductor substrate and having a second gate dielectric formed in a second high temperature process step and having a metallic gate conductor. The first and second high temperature process steps are performed before a step of forming the metallic gate conductor.
