US Patent 12069850 Semiconductor structure, manufacturing method thereof, and memory having bit line conducting layers covering the bit line contact layer and the insulating layer

A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, in which a plurality of active areas arranged in an array are provided; buried word lines located in the substrate, in which each of the active areas intersects with two of the buried word lines; grooves located in an upper surface of the substrate, in which each of the grooves is located between two of the buried word lines in each of the active areas; bit line contact layers filling the grooves; insulating layers distributed between two of the grooves, in which a thickness between upper surfaces of the insulating layers and the upper surface of the substrate is smaller than a thickness between upper surfaces of the bit line contact layers and the upper surface of the substrate; and bit line conducting layers, covering the bit line contact layers and the insulating layers.