US Patent 7476926 Eraseable nonvolatile memory with sidewall storage
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Patent Inventor Names
Chung H. Lam0
Jeffrey B. Johnson0
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Patent abstract
A nonvolatile storage cell and an integrated circuit (IC) including the cells. A layered spacer (ONO) is formed at least at one sidewall of cell gates. Source/drain diffusions at each layered spacer underlap the adjacent gate. Charge may be stored at a layer (an imbedded nitride layer) in the layered spacer.
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US Patent 07476926 Eraseable nonvolatile memory with sidewall storage US Patent 7476926 Eraseable nonvolatile memory with sidewall storage
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Patent Number
074769260
Patent Number
74769260
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Patent Jurisdiction
Patent Number
074769260
Date of Patent
January 13, 2009
0Patent Application Number
109054750
Date Filed
January 6, 2005
0Official Website
Patent Primary Examiner
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US Patent 07476926 Eraseable nonvolatile memory with sidewall storage
Infobox
Is a
Patent jurisdiction
Patent number
07476926
Date of patent
January 13, 2009
Patent application number
10905475
Date Filed
January 6, 2005
Patent primary examiner
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