US Patent 7474000 High density contact to relaxed geometry layers

Patent 7474000 was granted and assigned to SanDisk on January, 2009 by the United States Patent and Trademark Office.

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Patent Citations Received

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US Patent 11836277 Secure circuit integrated with memory layer

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Patent Inventor Names

Christopher J Petti0

Roy E Scheuerlein0

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Patent abstract

The present invention provides for a via and staggered routing level structure. Vertically overlapping vias connect to two or more routing levels formed at different heights. The routing levels are either both formed above or both formed below the vias, and all are formed above a semiconductor substrate wafer. In this way vias can be formed having a pitch smaller than the pitch of either the first routing level or the second routing level, saving space.

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Official Website

https://pdfpiw.uspto.gov/.piw?Docid=074740000

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