Is a
Patent attributes
Current Assignee
Patent Jurisdiction
Patent Number
Patent Inventor Names
Christopher J Petti0
Roy E Scheuerlein0
Date of Patent
January 6, 2009
0Patent Application Number
107284510
Date Filed
December 5, 2003
0Patent Citations Received
Patent Primary Examiner
Patent abstract
The present invention provides for a via and staggered routing level structure. Vertically overlapping vias connect to two or more routing levels formed at different heights. The routing levels are either both formed above or both formed below the vias, and all are formed above a semiconductor substrate wafer. In this way vias can be formed having a pitch smaller than the pitch of either the first routing level or the second routing level, saving space.
Timeline
No Timeline data yet.
Further Resources
No Further Resources data yet.
