Log in
Enquire now
‌

US Patent 7263602 Programmable pipeline fabric utilizing partially global configuration buses

Patent 7263602 was granted and assigned to Carnegie Mellon University on August, 2007 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors

Contents

Is a
Patent
Patent
0

Patent attributes

Current Assignee
Carnegie Mellon University
Carnegie Mellon University
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
72636020
Patent Inventor Names
Herman Schmit0
Date of Patent
August 28, 2007
0
Patent Application Number
102226450
Date Filed
August 16, 2002
0
Patent Citations Received
‌
US Patent 11880687 System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network
0
‌
US Patent 11907157 Reconfigurable processor circuit architecture
0
‌
US Patent 11886377 Reconfigurable arithmetic engine circuit
0
‌
US Patent 12106099 Execution or write mask generation for data selection in a multi-threaded, self-scheduling reconfigurable computing fabric
0
‌
US Patent 11977509 Reconfigurable processor circuit architecture
0
‌
US Patent 11915057 Computational partition for a multi-threaded, self-scheduling reconfigurable computing fabric
0
‌
US Patent 11868163 Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric
0
Patent Primary Examiner
‌
Eric Coleman
0
Patent abstract

A method of associating virtual stripes to physical stripes in a pipelined or ring structure comprises associating a first set of virtual stripes with at least two physical stripes and associating a second set of virtual stripes, disjoint from the first set, with at least two additional physical stripes. The present invention is also directed to a method of configuring a plurality of processing elements based on a less than global, but not purely local, association. The configuration method of the present invention may be implemented in a device arranged in stripes of processing elements. The method comprises configuring either of at least two physical stripes with a virtual stripe from a first set of virtual stripes and configuring either of at least two additional physical stripes with a virtual stripe from a second set of virtual stripes, said first and second virtual sets being disjoint. The present invention is also directed to a reconfigurable device comprising a controller, a memory device responsive to the controller, a plurality of processing elements arranged in stripes, a plurality of intra-stripe interconnections for connecting processing elements within a stripe, a plurality of local inter-stripe connections for connecting the output of one stripe to the input of one and only one other stripe, a plurality of global inter-stripe connections for connecting at least one but less than all of the physical stripes to the memory, and an input bus and an output bus, each connected to at least one physical stripe.

Timeline

No Timeline data yet.

Further Resources

Title
Author
Link
Type
Date
No Further Resources data yet.

References

Find more entities like US Patent 7263602 Programmable pipeline fabric utilizing partially global configuration buses

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
Open Query Tool
Access by API
Golden Query Tool
Golden logo

Company

  • Home
  • Press & Media
  • Blog
  • Careers
  • WE'RE HIRING

Products

  • Knowledge Graph
  • Query Tool
  • Data Requests
  • Knowledge Storage
  • API
  • Pricing
  • Enterprise
  • ChatGPT Plugin

Legal

  • Terms of Service
  • Enterprise Terms of Service
  • Privacy Policy

Help

  • Help center
  • API Documentation
  • Contact Us
By using this site, you agree to our Terms of Service.