US Patent 7132725 Semiconductor device
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Patent Inventor Names
Akio Iwabuchi0
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Patent abstract
A p-channel MOSFET 1 has a buried layer 9 between a substrate 2 and an epitaxial layer 3. The impurity concentration of the buried layer 9 is higher than that of the epitaxial layer 3. As a result, if the p-channel MOSFET 3 and an n-channel MOSFET are fabricated in a single semiconductor substrate and when a voltage is applied between the source electrode 13 and the drain electrode 12, the impurity concentration of the epitaxial layer 3 apparently increases. Thus, the charge balance of the p-channel MOSFET 1 is not lost.
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US Patent 07132725 Semiconductor device US Patent 7132725 Semiconductor device
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Patent Number
071327250
Patent Number
71327250
Edits on 25 Sep, 2022
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Patent Jurisdiction
Patent Number
071327250
Date of Patent
November 7, 2006
0Patent Application Number
105048910
Date Filed
February 24, 2003
0Official Website
Patent Primary Examiner
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US Patent 07132725 Semiconductor device
Infobox
Is a
Patent jurisdiction
Patent number
07132725
Date of patent
November 7, 2006
Patent application number
10504891
Date Filed
February 24, 2003
Patent primary examiner
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