Log in
Enquire now
‌

US Patent 12133390 Memory array

Patent 12133390 was granted and assigned to Taiwan Semiconductor Manufacturing Company on October, 2024 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors

Contents

Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
0
Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
0
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
121333900
Patent Inventor Names
Yu-Ming Lin0
Chao-I Wu0
Sai-Hooi Yeong0
Date of Patent
October 29, 2024
0
Patent Application Number
181705570
Date Filed
February 17, 2023
0
Patent Citations
‌
US Patent 9105490 Contact structure of semiconductor device
0
‌
US Patent 9236267 Cut-mask patterning process for fin-like field effect transistor (FinFET) device
0
‌
US Patent 9236300 Contact plugs in SRAM cells and the method of forming the same
0
‌
US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
0
‌
US Patent 9520482 Method of cutting metal gate
0
‌
US Patent 8772109 Apparatus and method for forming semiconductor contacts
0
‌
US Patent 8785285 Semiconductor devices and methods of manufacture thereof
0
‌
US Patent 8816444 System and methods for converting planar design to FinFET design
0
...
Patent Primary Examiner
‌
Matthew E Warren
0
CPC Code
‌
H01L 29/518
0
‌
H01L 29/517
0
‌
H01L 29/516
0
‌
H01L 29/40111
0
Patent abstract

Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

Timeline

No Timeline data yet.

Further Resources

Title
Author
Link
Type
Date
No Further Resources data yet.

References

Find more entities like US Patent 12133390 Memory array

Use the Golden Query Tool to find similar entities by any field in the Knowledge Graph, including industry, location, and more.
Open Query Tool
Access by API
Golden Query Tool
Golden logo

Company

  • Home
  • Press & Media
  • Blog
  • Careers
  • WE'RE HIRING

Products

  • Knowledge Graph
  • Query Tool
  • Data Requests
  • Knowledge Storage
  • API
  • Pricing
  • Enterprise
  • ChatGPT Plugin

Legal

  • Terms of Service
  • Enterprise Terms of Service
  • Privacy Policy

Help

  • Help center
  • API Documentation
  • Contact Us
By using this site, you agree to our Terms of Service.