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US Patent 12132020 Low temperature bonded structures

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Is a
Patent
Patent
0

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
0
Patent Number
121320200
Patent Inventor Names
Jeremy Alfred Theil0
Laura Wills Mirkarimi0
Guilian Gao0
Rajesh Katkar0
Cyprian Emeka Uzoh0
Date of Patent
October 29, 2024
0
Patent Application Number
185391430
Date Filed
December 13, 2023
0
Patent Citations
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US Patent 10707087 Processing stacked substrates
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US Patent 11256004 Direct-bonded lamination for improved image clarity in optical devices
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US Patent 11264357 Mixed exposure for large die
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US Patent 11276676 Stacked devices and methods of fabrication
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US Patent 11329034 Direct-bonded LED structure contacts and substrate contacts
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US Patent 11348898 Systems and methods for releveled bump planes for chiplets
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US Patent 11355443 Dielets on flexible and stretchable packaging for microelectronics
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US Patent 11515279 Low temperature bonded structures
0
...
Patent Primary Examiner
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Scott B. Geyer
0
Patent abstract

Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.

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