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US Patent 12131942 Source/drain isolation structure and methods thereof
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Patent
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Date Filed
June 30, 2023
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Date of Patent
October 29, 2024
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Patent Application Number
18344965
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Patent Citations
US Patent 8785285 Semiconductor devices and methods of manufacture thereof
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US Patent 8816444 System and methods for converting planar design to FinFET design
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US Patent 8823065 Contact structure of semiconductor device
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US Patent 8860148 Structure and method for FinFET integrated with capacitor
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US Patent 8994119 Semiconductor device with gate stacks having stress and method of manufacturing the same
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US Patent 9236267 Cut-mask patterning process for fin-like field effect transistor (FinFET) device
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US Patent 9236300 Contact plugs in SRAM cells and the method of forming the same
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US Patent 9405490 Electronic apparatus, management server, print system and method of controlling printing including determining a plurality of storages to store print data
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US Patent 9576814 Method of spacer patterning to form a target integrated circuit pattern
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US Patent 9520482 Method of cutting metal gate
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•••
Patent Inventor Names
Sheng-Tsung Wang
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Chih-Hao Wang
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Chia-Hao Chang
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Yu-Ming Lin
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Tien-Lu Lin
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Lin-Yu Huang
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
12131942
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Patent Primary Examiner
Peniel M Gumedzoe
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CPC Code
H01L 27/0886
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H01L 21/31144
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H01L 21/76224
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