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US Patent 12130885 Emulating fine-grained sparsity in a systolic array

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
November 3, 2022
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Date of Patent
October 29, 2024
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Patent Application Number
18052527
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Patent Citations
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US Patent 11194549 Matrix multiplication system, apparatus and method
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US Patent 11379556 Apparatus and method for matrix operations
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US Patent 11500962 Emulating fine-grained sparsity in a systolic array
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US Patent 11709783 Tensor data distribution using grid direct-memory access (DMA) controller
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US Patent 11625453 Using shared data bus to support systolic array tiling
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US Patent 11803736 Fine-grained sparsity computations in systolic array
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US Patent 11003985 Convolutional neural network system and operation method thereof
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US Patent 11126690 Machine learning architecture support for block sparsity
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Patent Inventor Names
Vignesh Vivekraja
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Ron Diamant
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Thiam Khean Hah
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Paul Gilbert Meyer
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Randy Renfu Huang
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
12130885
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Patent Primary Examiner
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Tan V. Mai
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CPC Code
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G06N 3/04
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G06F 17/16
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