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US Patent 12125526 Memory with bitcell power boosting

Patent 12125526 was granted and assigned to Qualcomm on October, 2024 by the United States Patent and Trademark Office.

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 US Patent 12125526 Memory with bitcell power boosting

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Patent abstract

A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

Infobox
Is a
Patent
Patent
0
Patent Applicant
Qualcomm
Qualcomm
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Current Assignee
Qualcomm
Qualcomm
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
121255260
Patent Inventor Names
Anil Chowdary Kota0
Chi-Jui Chen0
Chulmin Jung0
Dhvani Sheth0
Xiao Chen0
Date of Patent
October 22, 2024
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Patent Application Number
176572310
Date Filed
March 30, 2022
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Patent Citations
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US Patent 7696812 Cooperative charge pump circuit and method
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US Patent 7742326 8T SRAM cell with higher voltage on the read WL
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US Patent 7840112 Gradually degrading multimedia recordings
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US Patent 8233342 Apparatus and method for implementing write assist for static random access memory arrays
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US Patent 8619463 Adaptive write bit line and word line adjusting mechanism for memory
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US Patent 9236116 Memory cells with read access schemes
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US Patent 9245595 System and method for performing SRAM access assists using VSS boost
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US Patent 9281311 Memory cell array including a write-assist circuit and embedded coupling capacitor and method of forming same
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US Patent 9343140 Boosted read write word line
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US Patent 9460776 SRAM voltage assist
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US Patent 9570118 Circuits, architectures, apparatuses, systems, algorithms, and methods for memory with multiple power supplies and/or multiple low power modes
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US Patent 9837144 Apparatus and method for controlling boost capacitance for low power memory circuits
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US Patent 9842634 Wordline negative boost write-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) write port(s), and related systems and methods
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US Patent 9865337 Write data path to reduce charge leakage of negative boost
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US Patent 9875790 Boost charge recycle for low-power memory
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US Patent 9921596 Power supply noise reduction circuit and power supply noise reduction method
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US Patent 10128846 Apparatus and method for data level shifting with boost assisted inputs for high speed and low voltage applications
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US Patent 10199092 Boost circuit for memory
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US Patent 10381054 Common boosted assist
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US Patent 10553274 Low active power write driver with reduced-power boost circuit
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US Patent 10614865 Boost generation circuitry for memory
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US Patent 11049552 Write assist circuitry for memory
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US Patent 11568904 Memory with positively boosted write multiplexer
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US Patent 11651816 Memory unit
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US Patent 11657238 Low-power compute-in-memory bitcell
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US Patent 6845046 Microcomputer and microprocessor having flash memory operable from single external power supply
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Patent Primary Examiner
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Leon Viet Q Nguyen
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CPC Code
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G11C 11/419
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G11C 11/412
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