Patent attributes
Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.
