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US Patent 12107165 Semiconductor device structure with cap layer

Patent 12107165 was granted and assigned to Taiwan Semiconductor Manufacturing Company on October, 2024 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
121071650
Patent Inventor Names
Feng-Ching Chu0
Wei-Yang Lee0
Yen-Ming Chen0
Feng-Cheng Yang0
Date of Patent
October 1, 2024
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Patent Application Number
180683740
Date Filed
December 19, 2022
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Patent Citations
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US Patent 9093530 Fin structure of FinFET
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US Patent 8796666 MOS devices with strain buffer layer and methods of forming the same
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US Patent 8815712 Method for epitaxial re-growth of semiconductor region
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US Patent 8963258 FinFET with bottom SiGe layer in source/drain
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US Patent 9397102 III-V layers for N-type and P-type MOS source-drain contacts
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US Patent 9443757 Semiconductor device and method for fabricating the same
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US Patent 9450094 Semiconductor process and fin-shaped field effect transistor
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US Patent 9472613 Conversion of strain-inducing buffer to electrical insulator
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...
Patent Primary Examiner
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Bac H Au
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CPC Code
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H01L 29/41791
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H01L 29/7848
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H01L 21/823814
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H01L 29/66795
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H01L 29/785
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H01L 27/0924
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H01L 21/823821
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H01L 27/0886
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Patent abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure extended above a substrate along a first direction, and a first gate structure formed over the first fin structure along a second direction. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first fin structure and adjacent to the first gate structure, and a cap layer formed on and in direct contact with the first S/D structure. The semiconductor device structure includes an isolation structure formed adjacent to the first gate structure and the first S/D structure along the first direction, and a bottom surface of the isolation structure is lower than a bottom surface of the first gate structure and a bottom surface of the first S/D structure.

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