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US Patent 12067406 Multiple overlays for use with a data processing array

Patent 12067406 was granted and assigned to Xilinx Inc on August, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
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Xilinx Inc
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Current Assignee
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Xilinx Inc
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120674060
Patent Inventor Names
Dylan Stuart0
David Clarke0
Stephan Münz0
Pedro Miguel Parola Duarte0
Juan J. Noguera Serra0
Peter McColgan0
Baris Ozgul0
Date of Patent
August 20, 2024
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Patent Application Number
178198790
Date Filed
August 15, 2022
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Patent Citations
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US Patent 7199608 Programmable logic device and method of configuration
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US Patent 7224184 High bandwidth reconfigurable on-chip network for reconfigurable systems
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US Patent 7281093 Memory apparatus for a message processing system and method of providing same
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US Patent 7301822 Multi-boot configuration of programmable devices
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US Patent 7302625 Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration
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US Patent 7454658 In-system signal analysis using a programmable logic device
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US Patent 7328335 Bootable programmable logic device for internal decoding of encoded configuration data
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US Patent 7380035 Soft injection rate control for buses or network-on-chip with TDMA capability
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...
Patent Primary Examiner
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Farley Abad
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Patent abstract

Using multiple overlays with a data processing array includes loading an application in a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The application specifies kernels executable by the processors and implements stream channels that convey data to the plurality of compute tiles. During runtime of the application, a plurality of overlays are sequentially implemented in the data processing array. Each overlay implements a different mode of data movement in the data processing array via the stream channels. For each overlay implemented, a workload is performed by moving data to the plurality of compute tiles based on the respective mode of data movement.

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