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US Patent 12027211 Partial block handling protocol in a non-volatile memory device

Patent 12027211 was granted and assigned to Micron Technology on July, 2024 by the United States Patent and Trademark Office.

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Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Micron Technology
Micron Technology
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Current Assignee
Micron Technology
Micron Technology
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
120272110
Patent Inventor Names
Tingjun Xie0
Zhongguang Xu0
Murong Lang0
Date of Patent
July 2, 2024
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Patent Application Number
178254390
Date Filed
May 26, 2022
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Patent Citations
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US Patent 8503250 High speed DRAM architecture with uniform access latency
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Patent Primary Examiner
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Michael T. Tran
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CPC Code
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G11C 16/3404
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G11C 16/32
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G11C 16/26
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G11C 16/08
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G11C 16/102
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Patent abstract

A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device. The block includes a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data. The one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to concurrently program a remaining set of the plurality of wordlines of the block to a threshold voltage.

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