Patent attributes
A memory module comprises dynamic random access memory (DRAM) devices arranged in ranks, and a module controller configurable to receive address and control signals for a memory operation, and to output first module control signals to the DRAM devices, causing a selected rank to output or receive N-bit-wide data. The module controller is further configurable to output second module control signals to a plurality of data buffers coupled to the DRAM devices via module data lines. Each respective data buffer includes a n-bit-wide (n<N) data path and logic configurable to, in response to the second module control signals, enable the n-bit-wide data path to receive and regenerate signals carrying a respective n-bit-wide section of the N-bit-wide data communicated from/to a respective n-bit-wide section of the module data lines. The logic is further configurable to disable the n-bit-wide data path when the memory module is not being accessed for data.
