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US Patent 11942557 Nanosheet transistor with enhanced bottom isolation
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Patent
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Date Filed
May 3, 2021
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Date of Patent
March 26, 2024
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Patent Application Number
17246762
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Patent Citations
US Patent 9947804 Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
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US Patent 9984936 Methods of forming an isolated nano-sheet transistor device and the resulting device
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US Patent 10074575 Integrating and isolating nFET and pFET nanosheet transistors on a substrate
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US Patent 10170638 Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer
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US Patent 10312323 Bulk nanosheet with dielectric isolation
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US Patent 10361269 Forming bottom isolation layer for nanosheet technology
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US Patent 10461154 Bottom isolation for nanosheet transistors on bulk substrate
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US Patent 10453824 Structure and method to form nanosheet devices with bottom isolation
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US Patent 10818792 Nanosheet field-effect transistors formed with sacrificial spacers
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US Patent 9620590 Nanosheet channel-to-source and drain isolation
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•••
Patent Inventor Names
Wenyu Xu
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Lan Yu
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Heng Wu
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Andrew M. Greene
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11942557
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Patent Primary Examiner
Walter H Swanson
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CPC Code
H01L 29/0665
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H01L 29/0673
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H01L 29/41775
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H01L 29/78696
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