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US Patent 11929337 3D-interconnect

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
June 7, 2021
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Date of Patent
March 12, 2024
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Patent Application Number
17340469
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Patent Citations
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US Patent 8035192 Semiconductor device and manufacturing method thereof
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US Patent 8482111 Stackable molded microelectronic packages
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US Patent 8492203 Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
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US Patent 8557700 Method for manufacturing a chip-size double side connection package
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US Patent 8641913 Fine pitch microcontacts and method for forming thereof
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US Patent 8692135 Wiring board capable of containing functional element and method for manufacturing same
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US Patent 8709933 Interposer having molded low CTE dielectric
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US Patent 8736066 Stacked microelectronic assemby with TSVS formed in stages and carrier above chip
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US Patent 8841765 Multi-chip module with stacked face-down connected dies
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US Patent 8883563 Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
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•••
Patent Inventor Names
Patrick Variot
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Qwai H. Low
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Chok J. Chia
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11929337
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Patent Primary Examiner
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S M Sohel Imtiaz
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CPC Code
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H01L 25/0652
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H01L 24/81
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H01L 21/52
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H01L 23/5386
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H01L 21/568
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H01L 24/17
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H01L 23/5389
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H01L 2224/02331
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H01L 2224/0401
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H01L 24/19
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•••

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