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US Patent 11908784 Packaged semiconductor device assembly
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Patent
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Date Filed
September 23, 2020
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Date of Patent
February 20, 2024
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Patent Application Number
17029680
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Patent Citations
US Patent 8788741 Method and apparatus adapted to prevent code data from being lost in solder reflow
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US Patent 9064858 Semiconductor device and method of forming bump-on-lead interconnection
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US Patent 9651751 Compact optical transceiver by hybrid multichip integration
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US Patent 9245770 Semiconductor device and method of simultaneous molding and thermalcompression bonding
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US Patent 9755335 Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction
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US Patent 8413321 Module substrate and production method
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US Patent 8471376 Integrated circuit packaging configurations
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Patent Inventor Names
Nishant Lakhera
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Nihaar N. Mahatme
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Chee Seng Foong
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Akhilesh Kumar Singh
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Andrew Jefferson Mawer
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11908784
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Patent Primary Examiner
Michele Fan
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CPC Code
H01L 23/5383
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H01L 23/49811
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H01L 23/49833
0
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