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US Patent 9064858 Semiconductor device and method of forming bump-on-lead interconnection

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Patent
Patent
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Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
90648580
Patent Inventor Names
Rajendra D. Pendse0
Date of Patent
June 23, 2015
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Patent Application Number
140219140
Date Filed
September 9, 2013
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Patent Citations Received
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US Patent 11894329 Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars
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‌
US Patent 11908784 Packaged semiconductor device assembly
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Patent Primary Examiner
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Hsien-Ming Lee
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Patent abstract

A semiconductor device has a semiconductor die with a plurality of composite bumps formed over a surface of the semiconductor die. The composite bumps have a fusible portion and non-fusible portion, such as a conductive pillar and bump formed over the conductive pillar. The composite bumps can also be tapered. Conductive traces are formed over a substrate with interconnect sites having edges parallel to the conductive trace from a plan view for increasing escape routing density. The interconnect site can have a width less than 1.2 times a width of the conductive trace. The composite bumps are wider than the interconnect sites. The fusible portion of the composite bumps is bonded to the interconnect sites so that the fusible portion covers a top surface and side surface of the interconnect sites. An encapsulant is deposited around the composite bumps between the semiconductor die and substrate.

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