Patent attributes
An in-memory computation (IMC) circuit includes a memory array formed by memory cells arranged in row-by-column matrix. Computational weights for an IMC operation are stored in the memory cells. Each column includes a bit line connected to the memory cells. A biasing circuit is connected between each bit line and a corresponding column output. A column combining circuit combines and integrates analog signals at the column outputs of the biasing circuits. Each biasing circuit operates to apply a fixed reference voltage level to its bit line. Each biasing circuit further includes a switching circuit that is controlled to turn on for a time duration controlled by asps comparison of a coefficient data signal to a ramp signal to generate the analog signal dependent on the computational weight. The ramp signal is generated using a reference current derived from a reference memory cell.
