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US Patent 11893425 Disaggregated computing for distributed confidential computing environment

Patent 11893425 was granted and assigned to Intel on February, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
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Patent attributes

Patent Applicant
Intel
Intel
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Current Assignee
Intel
Intel
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
118934250
Patent Inventor Names
Reshma Lal0
Luis Kida0
Pradeep Pappachan0
Robert Sharp0
Sujoy Sen0
Selvakumar Panneer0
Soham Jayesh Desai0
Date of Patent
February 6, 2024
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Patent Application Number
175310050
Date Filed
November 19, 2021
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Patent Citations
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US Patent 10528765 Technologies for secure boot provisioning and management of field-programmable gate array images
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US Patent 10776145 Systems and methods for traffic monitoring in a virtualized software defined storage architecture
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US Patent 11449963 Virtual graphics processing with remote execution
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US Patent 7971236 Method and system for secure remote direct memory access
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US Patent 8930717 Secure processing module and method for making the same
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US Patent 10482291 Secure field-programmable gate array (FPGA) architecture
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US Patent 10649790 Multithreaded rendering for virtualized graphics processing
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US Patent 10652108 Techniques to establish service level agreements or quality of service for remotely accessible storage devices
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Patent Citations Received
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US Patent 12093748 Disaggregated computing for distributed confidential computing environment
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Patent Primary Examiner
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Sisley N Kim
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CPC Code
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G06T 1/60
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G06T 1/20
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G06F 21/53
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G06F 9/5077
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H04L 9/3234
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G06F 9/5027
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G06F 9/3814
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G06F 9/5083
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Patent abstract

An apparatus to facilitate disaggregated computing for a distributed confidential computing environment is disclosed. The apparatus includes a processor executing a trusted execution environment (TEE) comprising a field-programmable gate array (FPGA) driver to interface with an FPGA device that is remote to the apparatus; and a remote memory-mapped input/output (MMIO) driver to expose the FPGA device as a legacy device to the FPGA driver, wherein the processor to utilize the remote MMIO driver to: enumerate the FPGA device using FPGA enumeration data provided by a remote management controller of the FPGA device, the FPGA enumeration data comprising a configuration space and device details; load function drivers for the FPGA device in the TEE; create corresponding device files in the TEE based on the FPGA enumeration data; and handle remote MMIO reads and writes to the FPGA device via a network transport protocol.

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