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US Patent 11887975 Semiconductor device manufacturing method

Patent 11887975 was granted and assigned to Daicel on January, 2024 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent
0

Patent attributes

Patent Applicant
Daicel
Daicel
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Current Assignee
Daicel
Daicel
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
118879750
Patent Inventor Names
Naoko Tsuji0
Date of Patent
January 30, 2024
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Patent Application Number
172879220
Date Filed
October 18, 2019
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Patent Citations
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US Patent 9960080 Method for bonding and interconnecting integrated circuit devices
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US Patent 10014292 3D semiconductor device and structure
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US Patent 10163864 Vertically stacked wafers and methods of forming same
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US Patent 10947425 Adhesive
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US Patent 10964576 Electrostatic attachment chuck, method for manufacturing the same, and semiconductor device manufacturing method
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US Patent 11069560 Method of transferring device layer to transfer substrate and highly thermal conductive substrate
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US Patent 9543257 3DIC interconnect devices and methods of forming same
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US Patent 8415807 Semiconductor structure and method for making the same
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Patent Primary Examiner
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Vu A Vu
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CPC Code
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H01L 21/185
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H01L 21/02164
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H01L 21/02
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H01L 25/074
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H01L 2221/68359
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C08L 83/06
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C09J 135/08
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C09J 2203/326
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Patent abstract

Provided is a semiconductor device manufacturing method in which semiconductor elements are formed into multiple layers through the lamination of wafers in which the semiconductor elements are fabricated, the method being suited for efficiently creating multiple layers of thin wafers while suppressing warping of a wafer laminate. The method of the present invention includes a preparation step, a thinning step, a bonding step, a removal step, and a multilayering step. In the preparation step, a reinforced wafer is prepared, the reinforced wafer having a laminated structure that includes: a wafer including an element forming surface and a back surface opposite from the element forming surface; a supporting substrate; and a temporary adhesive layer for forming temporary adhesion, the temporary adhesive layer being provided between the element forming surface side of the wafer and the supporting substrate.

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