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US Patent 10014292 3D semiconductor device and structure

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Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10014292
Date of Patent
July 3, 2018
Patent Application Number
15477106
Date Filed
April 2, 2017
Patent Citations Received
‌
US Patent 12087679 Package core assembly and fabrication methods
0
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US Patent 11476268 Methods of forming electronic devices using materials removable at different temperatures
0
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US Patent 12069856 Methods of forming electronic devices using materials removable at different temperatures
0
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US Patent 11476202 Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration
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US Patent 10115681 Compact three-dimensional memory device having a seal ring and methods of manufacturing the same
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US Patent 11521935 Package structure and fabrication methods
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US Patent 11521937 Package structures with built-in EMI shielding
...
Patent Primary Examiner
‌
Tu-Tu Ho
Patent abstract

A 3D semiconductor device, the device including: a first die including a first transistors layer and a first interconnection layer; and a second die overlaying the first die, the second die including a second transistors layer and a second interconnection layer, where the second die thickness is less than 2 microns, and where the first die is substantially larger than the second die.

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