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US Patent 11862235 Stacked semiconductor device

Patent 11862235 was granted and assigned to Rambus on January, 2024 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
Rambus
Rambus
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Date Filed
October 22, 2021
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Date of Patent
January 2, 2024
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Patent Applicant
Rambus
Rambus
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Patent Application Number
17508861
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Patent Citations
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US Patent 7898834 Semiconductor chip with chip selection structure and stacked semiconductor package having the same
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US Patent 8233303 Multi-die memory device
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US Patent 8258619 Integrated circuit die stacks with translationally compatible vias
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US Patent 8432027 Integrated circuit die stacks with rotationally symmetric vias
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US Patent 8436477 Stub minimization using duplicate sets of signal terminals in assemblies without wirebonds to package substrate
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US Patent 8513817 Memory module in a package
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US Patent 9432298 System, method, and computer program product for improving memory systems
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US Patent 7071546 Space-saving packaging of electronic circuits
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US Patent 7098541 Interconnect method for directly connected stacked integrated circuits
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US Patent 7208343 Semiconductor chip, chip stack package and manufacturing method
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•••
Patent Inventor Names
Frederick A. Ware
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11862235
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Patent Primary Examiner
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Han Yang
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CPC Code
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G11C 17/16
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G11C 5/04
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G11C 11/4093
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G11C 17/18
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G11C 11/4096
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