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US Patent 11841395 Integrated circuit margin measurement and failure prediction device

Patent 11841395 was granted and assigned to ProteanTecs on December, 2023 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Current Assignee
ProteanTecs
ProteanTecs
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Date Filed
July 11, 2022
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Date of Patent
December 12, 2023
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Patent Applicant
ProteanTecs
ProteanTecs
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Patent Application Number
17862142
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Patent Citations
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US Patent 7254507 Analog circuit automatic calibration system
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US Patent 6873926 Methods and apparatus for testing a clock signal
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US Patent 6882172 System and method for measuring transistor leakage current with a ring oscillator
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US Patent 6948388 Wireless remote sensor
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US Patent 7038483 System and method for measuring transistor leakage current with a ring oscillator
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US Patent 7067335 Apparatus and methods for semiconductor IC failure detection
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US Patent 9791834 Fast digital to time converter linearity calibration to improve clock jitter performance
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US Patent 9954455 Constant on time COT control in isolated converter
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US Patent 9991879 Apparatus for detecting variation in transistor threshold voltage
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US Patent 10490547 IC with larger and smaller width contacts
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•••
Patent Inventor Names
Shai Cohen
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Eyal Fayneh
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Evelyn Landman
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Yahel David
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Inbar Weintrob
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11841395
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Patent Primary Examiner
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Jermele M Hollington
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