US Patent 11804522 Sidewall epitaxy encapsulation for nanosheet I/O device

A semiconductor structure includes a first nanosheet fin extending vertically from a first region of a substrate corresponding to a logic device and a second nanosheet fin extending vertically from a second region of the substrate corresponding to an input/output device. The first nanosheet fin includes first semiconductor channel layers vertically stacked over the first region of the substrate, while the second nanosheet fin includes an alternating sequence of semiconductor sacrificial layers and second semiconductor channel layers. The semiconductor structure further includes an epitaxially grown encapsulation layer disposed only along sidewalls of the second nanosheet fin.