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US Patent 11784228 Process and structure for source/drain contacts

Patent 11784228 was granted and assigned to Taiwan Semiconductor Manufacturing Company on October, 2023 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
Current Assignee
Taiwan Semiconductor Manufacturing Company
Taiwan Semiconductor Manufacturing Company
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11784228
Patent Inventor Names
Meng-Huan Jao
Huan-Chieh Su
Sheng-Tsung Wang
Cheng-Chi Chuang
Lin-Yu Huang
Chih-Hao Wang
Date of Patent
October 10, 2023
Patent Application Number
17338384
Date Filed
June 3, 2021
Patent Citations
‌
US Patent 8816444 System and methods for converting planar design to FinFET design
‌
US Patent 8823065 Contact structure of semiconductor device
‌
US Patent 8836016 Semiconductor structures and methods with high mobility and high energy bandgap materials
‌
US Patent 8841701 FinFET device having a channel defined in a diamond-like shape semiconductor structure
‌
US Patent 8847293 Gate structure for semiconductor device
‌
US Patent 8772109 Apparatus and method for forming semiconductor contacts
‌
US Patent 8785285 Semiconductor devices and methods of manufacture thereof
‌
US Patent 8802504 3D packages and methods for forming the same
...
Patent Primary Examiner
‌
Reema Patel
CPC Code
‌
H01L 21/3212
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H01L 21/31138
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H01L 21/31144
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H01L 29/41775
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H01L 29/41725
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H01L 29/45
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H01L 29/401
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H01L 29/42392
...
Patent abstract

A method includes providing a structure having source/drain electrodes and a first dielectric layer over the source/drain electrodes; forming a first etch mask covering a first area of the first dielectric layer; performing a first etching process to the first dielectric layer, resulting in first trenches over the source/drain electrodes; filling the first trenches with a second dielectric layer that has a different material than the first dielectric layer; removing the first etch mask; performing a second etching process including isotropic etching to the first area of the first dielectric layer, resulting in a second trench above a first one of the source/drain electrodes; depositing a metal layer into at least the second trench; and performing a chemical mechanical planarization (CMP) process to the metal layer.

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