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US Patent 11776602 Memory array staircase structure

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
Date Filed
July 22, 2022
Date of Patent
October 3, 2023
Patent Application Number
17814341
Patent Citations
‌
US Patent 9570464 Method for manufacturing semiconductor device
‌
US Patent 9620513 Semiconductor device and method of manufacturing the same
‌
US Patent 9620712 Concave word line and convex interlayer dielectric for protecting a read/write layer
‌
US Patent 9748257 Semiconductor devices having dummy patterns and methods of fabricating the same
‌
US Patent 9947721 Thermal insulation for three-dimensional memory arrays
‌
US Patent 9953992 Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof
‌
US Patent 10109639 Lateral non-volatile storage cell
‌
US Patent 10115681 Compact three-dimensional memory device having a seal ring and methods of manufacturing the same
‌
US Patent 10256248 Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
‌
US Patent 10283513 Three-dimensional memory device with annular blocking dielectrics and method of making thereof
•••
Patent Inventor Names
Sheng-Chen Wang
Meng-Han Lin
Han-Jong Chia
Feng-Cheng Yang
Chung-Te Lin
Yu-Ming Lin
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11776602
Patent Primary Examiner
‌
Fernando Hidalgo
CPC Code
‌
H01L 27/11578
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H01L 27/11551
‌
H01L 27/1159
‌
H01L 21/8221
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H01L 29/6684
‌
H01L 29/78391
‌
G11C 8/14
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H01L 27/11597

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