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US Patent 11714949 Leakage analysis on semiconductor device
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Patent
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Date Filed
May 7, 2021
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Date of Patent
August 1, 2023
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Patent Application Number
17314988
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Patent Citations
US Patent 8759885 Standard cell for semiconductor device
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US Patent 8836040 Shared-diffusion standard cell architecture
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US Patent 8863063 Finfet transistor circuit
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US Patent 8898614 Integrated circuit device with reduced leakage and method therefor
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US Patent 8943455 Methods for layout verification for polysilicon cell edge structures in FinFET standard cells
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US Patent 9009641 Circuits with linear finfet structures
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US Patent 9058462 System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE)
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US Patent 9318476 High performance standard cell with continuous oxide definition and characterized leakage current
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US Patent 9336346 Integral fabrication of asymmetric CMOS transistors for autonomous wireless state radios and sensor/actuator nodes
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US Patent 9336348 Method of forming layout design
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Patent Jurisdiction
United States Patent and Trademark Office
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Patent Number
11714949
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Patent Primary Examiner
Naum Levin
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CPC Code
G06F 30/33
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H01L 22/14
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H01L 22/20
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H01L 22/34
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H01L 27/0207
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H01L 23/528
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H01L 29/41725
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Y02P 90/02
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G06F 30/398
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G06F 30/20
0
•••
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