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US Patent 11704130 Indexing external memory in a reconfigurable compute fabric

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Is a
Patent
Patent
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Patent attributes

Patent Applicant
Micron Technology
Micron Technology
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Current Assignee
Micron Technology
Micron Technology
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
117041300
Date of Patent
July 18, 2023
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Patent Application Number
174028280
Date Filed
August 16, 2021
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Patent Citations
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US Patent 9710384 Microprocessor architecture having alternative memory access paths
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US Patent 10990392 Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric
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US Patent 10990391 Backpressure control using a stop signal for a multi-threaded, self-scheduling reconfigurable computing fabric
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US Patent 8122229 Dispatch mechanism for dispatching instructions from a host processor to a co-processor
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US Patent 8156307 Multi-processor system having at least one processor that comprises a dynamically reconfigurable instruction set
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US Patent 8205066 Dynamically configured coprocessor for different extended instruction set personality specific to application program with shared memory storing instructions invisibly dispatched from host processor
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US Patent 8423745 Systems and methods for mapping a neighborhood of data to general registers of a processing element
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US Patent 8561037 Compiler for generating an executable comprising instructions for a plurality of different instruction sets
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Patent Primary Examiner
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Jacob Petranek
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CPC Code
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G06F 9/3004
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G06F 9/355
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Various examples are directed to systems and methods in which a flow controller of a first synchronous flow may receive an instruction to execute a first loop using the first synchronous flow. The flow controller may determine a first iteration index for a first iteration of the first loop. The flow controller may send, to a first compute element of the first synchronous flow, a first synchronous message to initiate a first synchronous flow thread for executing the first iteration of the first loop. The first synchronous message may comprise the iteration index. The first compute element may execute an input/output operation at a first location of a first compute element memory indicated by the first iteration index.

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