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US Patent 11693808 Multi-die integrated circuit with data processing engine array

Patent 11693808 was granted and assigned to Xilinx on July, 2023 by the United States Patent and Trademark Office.

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
1
Current Assignee
Xilinx
Xilinx
1
Date Filed
March 11, 2022
1
Date of Patent
July 4, 2023
1
Patent Applicant
Xilinx
Xilinx
1
Patent Application Number
17654543
1
Patent Citations
‌
US Patent 7478357 Versatile bus interface macro for dynamically reconfigurable designs
1
‌
US Patent 7482836 High bandwidth reconfigurable on-chip network for reconfigurable systems
1
‌
US Patent 7509617 Design methodology to support relocatable bit streams for dynamic partial reconfiguration of FPGAs to reduce bit stream memory requirements
1
‌
US Patent 7518396 Apparatus and method for reconfiguring a programmable logic device
1
‌
US Patent 7640527 Method and apparatus for partial reconfiguration circuit design for a programmable device
1
‌
US Patent 7746099 Method of and system for implementing a circuit in a device having programmable logic
1
‌
US Patent 8045546 Configuring routing in mesh networks
1
‌
US Patent 8102188 Method of and system for implementing a circuit in a device having programmable logic
1
‌
US Patent 8250342 Digital signal processing engine
1
‌
US Patent 8359448 Specific memory controller implemented using reconfiguration
1
•••
Patent Citations Received
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US Patent 12015412 Dual phase clock distribution from a single source in a die-to-die interface
2
‌
US Patent 11960435 Skew matching in a die-to-die interface
3
‌
US Patent 12001367 Multi-die integrated circuit with data processing engine array
4
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
11693808
1
Patent Primary Examiner
‌
Michael Sun
1
Industry
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