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US Patent 11675943 Tool to create a reconfigurable interconnect framework

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Is a
Patent
Patent
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Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
116759430
Date of Patent
June 13, 2023
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Patent Application Number
170947430
Date Filed
November 10, 2020
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Patent Citations
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US Patent 10078620 Runtime reconfigurable dataflow processor with multi-port memory access module
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US Patent 7737994 Large-kernel convolution using multiple industry-standard graphics accelerators
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US Patent 7840403 Entropy coding using escape codes to switch between plural code tables
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US Patent 8131659 Field-programmable gate array based accelerator system
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US Patent 9020276 Hardware coprocessor for stripe-based interest point detection
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US Patent 10296829 Convolution processing apparatus and method
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US Patent 10394929 Adaptive execution engine for convolution computing systems
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US Patent 10417364 Tool to create a reconfigurable interconnect framework
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Patent Primary Examiner
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Paul Dinh
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CPC Code
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G06F 9/44505
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G06F 13/4022
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G06F 15/7817
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G06F 2115/08
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G06N 3/0445
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G06N 3/0454
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G06N 3/0472
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G06N 3/084
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Embodiments are directed towards a method to create a reconfigurable interconnect framework in an integrated circuit. The method includes accessing a configuration template directed toward the reconfigurable interconnect framework, editing parameters of the configuration template, functionally combining the configuration template with a plurality of modules from an IP library to produce a register transfer level (RTL) circuit model, generating at least one automated test-bench function, and generating at least one logic synthesis script. Editing parameters of the configuration template includes confirming a first number of output ports of a reconfigurable stream switch and confirming a second number of input ports of the reconfigurable stream switch. Each output port and each input port has a respective architectural composition. The output port architectural composition is defined by a plurality of N data paths including A data outputs and B control outputs. The input port architectural composition is defined by a plurality of M data paths including A data inputs and B control inputs.

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