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US Patent 11538781 Integrated device packages including bonded structures

Overview Structured Data Issues Contributors Activity

Is a

Date Filed

December 28, 2021

Date of Patent

December 27, 2022

Patent Application Number

17646238

Patent Citations

US Patent 10204893 Stacked dies and methods for forming bonded structures

US Patent 10276619 Semiconductor device structure with a conductive feature passing through a passivation layer

US Patent 10276909 Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein

US Patent 10418277 Air gap spacer formation for nano-scale semiconductor devices

US Patent 10446456 Integrated circuits protected by substrates with cavities, and methods of manufacture

US Patent 10707087 Processing stacked substrates

US Patent 10727204 Die stacking for multi-tier 3D integration

US Patent 10727219 Techniques for processing devices

US Patent 10790262 Low temperature bonded structures

US Patent 10879212 Processed stacked dies

•••

Patent Citations Received

US Patent 12113056 Stacked dies and methods for forming bonded structures

0

US Patent 11955463 Direct bonded stack structures for increased reliability and improved yield in microelectronics

0

Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Patent Primary Examiner

Didarul A Mazumder

CPC Code

H01L 2224/08145

H01L 2224/80006

H01L 2224/80895

H01L 2224/80896

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