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US Patent 11521669 Semiconductor device having cam that stores address signals

Patent 11521669 was granted and assigned to Micron Technology on December, 2022 by the United States Patent and Trademark Office.

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Contents

Is a
Patent
Patent

Patent attributes

Patent Applicant
Micron Technology
Micron Technology
Current Assignee
Micron Technology
Micron Technology
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11521669
Date of Patent
December 6, 2022
Patent Application Number
17301533
Date Filed
April 6, 2021
Patent Citations
‌
US Patent 10153031 Apparatuses and methods for controlling refresh operations
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US Patent 10170174 Apparatus and methods for refreshing memory
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US Patent 10176860 Refresh in non-volatile memory
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US Patent 10210925 Row hammer refresh command
‌
US Patent 10297305 Memory device having twin cell mode and refresh method thereof
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US Patent 10339994 Semiconductor device
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US Patent 10381327 Non-volatile memory system with wide I/O memory die
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US Patent 10387276 Semiconductor memory devices with error correction and methods of operating the same
...
Patent Citations Received
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US Patent 11664063 Apparatuses and methods for countering memory attacks
0
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US Patent 11984148 Apparatuses and methods for tracking victim rows
0
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US Patent 11854618 Apparatuses, systems, and methods for determining extremum numerical values
0
‌
US Patent 11699476 Apparatuses and methods for monitoring word line accesses
0
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US Patent 11682444 Dynamic random-access memory array including sensor cells
0
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US Patent 11688451 Apparatuses, systems, and methods for main sketch and slim sketch circuit for row address tracking
0
Patent Primary Examiner
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Alfredo Bermudez Lozada
CPC Code
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G11C 11/40603
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G11C 11/406
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G11C 11/401
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G11C 11/408
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G11C 11/4085

An apparatus may include multiple address registers each storing an address signal and multiple counter circuits each storing a count value corresponding to an associated one of the address registers. The apparatus may include a first circuit cyclically selecting one of the address registers in response to a first signal, a second circuit selecting one of the address registers based on the count value of each of the counter circuits, and a third circuit activating a second signal when the first and second circuits select the same one of the address registers.

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