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US Patent 11507301 Memory module implementing memory centric architecture

Overview Structured Data Issues Contributors

Is a

Date Filed

February 16, 2021

Date of Patent

November 22, 2022

Patent Application Number

17176860

Patent Citations

US Patent 10121553 Capacitive-coupled non-volatile thin-film transistor NOR strings in three-dimensional arrays

US Patent 10249370 Three-dimensional vertical NOR flash thing-film transistor strings

US Patent 10254968 Hybrid memory device for lookup operations

US Patent 10283493 Three-dimensional memory device containing bonded memory die and peripheral logic die and method of making thereof

US Patent 10373956 Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors

US Patent 10381370 Semiconductor device

US Patent 10381378 Three-dimensional vertical NOR flash thin-film transistor strings

US Patent 10395737 Three-dimensional vertical NOR flash thin-film transistor strings

US Patent 10431596 Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays

US Patent 10622377 3-dimensional NOR memory array with very fine pitch: device and method

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Patent Jurisdiction

United States Patent and Trademark Office

Patent Number

Patent Primary Examiner

Christopher B. Shin

CPC Code

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