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US Patent 11418199 Phase locked loop with parallel phase detection circuits

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
0
Date Filed
May 21, 2021
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Date of Patent
August 16, 2022
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Patent Application Number
17327049
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Patent Citations Received
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US Patent 11990913 Systems and methods for providing a delay-locked loop with coarse tuning technique
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‌
US Patent 11601156 Apparatus and methods for improved transmit power
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US Patent 11876523 DPLL timing normalization
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US Patent 11569831 Time-to-digital converter calibration
Patent Inventor Names
Dmytro Cherniak
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Alessio Santiccioli
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Salvatore Levantino
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
11418199
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Patent Primary Examiner
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Diana J. Cheng
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CPC Code
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H03L 7/099
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H03L 7/0991
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H03L 2207/50
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H04L 7/0331
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H03L 7/089
0
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H03L 7/091
0
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H03L 7/087
0

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