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US Patent 11418199 Phase locked loop with parallel phase detection circuits

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Is a
Patent
Patent
1

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
1
Patent Number
114181991
Patent Inventor Names
Dmytro Cherniak1
Alessio Santiccioli1
Salvatore Levantino1
Date of Patent
August 16, 2022
1
Patent Application Number
173270491
Date Filed
May 21, 2021
1
Patent Citations Received
‌
US Patent 11990913 Systems and methods for providing a delay-locked loop with coarse tuning technique
2
‌
US Patent 11601156 Apparatus and methods for improved transmit power
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US Patent 11876523 DPLL timing normalization
4
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US Patent 11569831 Time-to-digital converter calibration
Patent Primary Examiner
‌
Diana J. Cheng
1
CPC Code
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H03L 7/099
1
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H03L 7/0991
1
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H03L 2207/50
1
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H04L 7/0331
1
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H03L 7/089
1
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H03L 7/091
1
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H03L 7/087
1

In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.

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