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Patent attributes
Patent Jurisdiction
Patent Number
Patent Inventor Names
Dmytro Cherniak1
Alessio Santiccioli1
Salvatore Levantino1
Date of Patent
August 16, 2022
1Patent Application Number
173270491
Date Filed
May 21, 2021
1Patent Citations Received
Patent Primary Examiner
In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.
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