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US Patent 11355516 Three-dimensional memory device and method

OverviewStructured DataIssuesContributors
Is a
Patent
Patent
Date Filed
September 11, 2020
Date of Patent
June 7, 2022
Patent Application Number
17018232
Patent Citations
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US Patent 10930333 Embedded ferroelectric memory cell
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US Patent 10115681 Compact three-dimensional memory device having a seal ring and methods of manufacturing the same
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US Patent 10593399 Self-selecting memory array with horizontal bit lines
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US Patent 10446437 Interlevel connectors in multilevel circuitry, and method for forming the same
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US Patent 10256248 Through-memory-level via structures between staircase regions in a three-dimensional memory device and method of making thereof
Patent Citations Received
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US Patent 12002534 Memory array word line routing
8
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US Patent 11647634 Three-dimensional memory device and method
9
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US Patent 11776602 Memory array staircase structure
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US Patent 11985830 Three-dimensional memory device and method
10
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US Patent 11532640 Method for manufacturing a three-dimensional memory
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
11355516
Patent Primary Examiner
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Karen Kusumakar
CPC Code
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H01L 21/7684
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H01L 21/76871
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H01L 27/11597
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H01L 23/5226
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H01L 27/1159
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H01L 21/76877
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H01L 21/32133
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H01L 21/76802

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