US Patent 11354193 Memory device with dynamic processing level calibration

A system includes a memory array including a plurality of memory cells; and a processing device coupled to the memory array, the processing device configured to iteratively adjust an active processing level used to process data, wherein, for each iteration, the processing device is configured to: determine a first error rate corresponding to the active processing level, determine a second error rate based on using an offset processing level different than the active processing level, and incrementally adjust the active processing level based on a comparison of the first error rate and the second error rate.