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US Patent 11276676 Stacked devices and methods of fabrication
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Is a
Patent
0
Date Filed
May 15, 2019
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Date of Patent
March 15, 2022
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Patent Application Number
16413429
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Patent Citations
US Patent 10075657 Edgeless large area camera system
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US Patent 10269756 Die processing
US Patent 10026605 Method of reducing residual contamination in singulated semiconductor die
US Patent 10276619 Semiconductor device structure with a conductive feature passing through a passivation layer
Patent Citations Received
US Patent 11631647 Integrated device packages with integrated device die and dummy element
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US Patent 11652083 Processed stacked dies
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US Patent 12136605 Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics and method for forming the same
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US Patent 11515202 3D IC method and device
US Patent 11515279 Low temperature bonded structures
US Patent 11600542 Cavity packages
US Patent 11610846 Protective elements for bonded structures including an obstructive element
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US Patent 11621246 Diffused bitline replacement in stacked wafer memory
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US Patent 11626363 Bonded structures with integrated passive component
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US Patent 11631586 Heterogeneous annealing method
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•••
Patent Inventor Names
Belgacem Haba
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Paul M. Enquist
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Patent Jurisdiction
United States Patent and Trademark Office
0
Patent Number
11276676
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Patent Primary Examiner
Scott B. Geyer
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CPC Code
H01L 25/074
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H01L 25/071
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H01L 25/0657
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H01L 25/0652
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H01L 25/043
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H01L 23/3157
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H01L 23/3185
0
H01L 23/3171
0
H01L 2225/06555
0
H01L 2225/06568
0
•••
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