US Patent 11159240 Power efficient and scalable co-packaged optical devices

A co-packaged optical-electrical chip can include an application-specific integrated circuit (ASIC) and a plurality of optical modules, such as optical transceivers. The ASIC and each of the optical modules can exchange electrical signaling via integrated electrical paths. The ASIC can include Ethernet switch, error correction, bit-to-symbol mapping/demapping, and digital signal processing circuits to pre-compensate and post-compensate channel impairments (e.g., inter-channel/intra-channel impairments) in electrical and optical domains. The co-packaged inter-chip interface can be scaled to handle different data rates using spectral efficient signaling formats (e.g., QAM-64, PAM-8) without adding additional data lines to a given design and without significantly increasing the power consumption of the design.