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US Patent 10784871 Clocking architecture for DVFS with low-frequency DLL locking

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US Patent 11927612 Digital droop detector
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https://pdfpiw.uspto.gov/.piw?Docid=10784871
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US Patent 11545987 Traversing a variable delay line in a deterministic number of clock cycles
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US Patent 11545981 DLL-based clocking architecture with programmable delay at phase detector inputs
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US Patent 11520371 Compute-adaptive clock management for machine learning accelerators
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US Patent 11522550 Semiconductor device including delay compensation circuit
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US Patent 11402413 Droop detection and mitigation
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US Patent 11290117 Low-frequency arithmetic multiplying PLL for HDL devices
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 US Patent 10784871 Clocking architecture for DVFS with low-frequency DLL locking

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10784871
Date of patent
September 22, 2020
Patent application number
16528381
Date Filed
July 31, 2019
Patent citations
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US Patent 10530370 Glitch-free PLL Multiplexer
Patent primary examiner
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Adam D Houston

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