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US Patent 10741456 Vertically stacked nanosheet CMOS transistor

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Patent Citations Received
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US Patent 11894378 Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance
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US Patent 11843001 Devices including stacked nanosheet transistors
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US Patent 11842919 Method of making 3D isolation
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Official Website
https://pdfpiw.uspto.gov/.piw?Docid=1074145600
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https://pdfpiw.uspto.gov/.piw?Docid=10741456
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 US Patent 10741456 Vertically stacked nanosheet CMOS transistor

Infobox
Is a
Patent
Patent
Patent jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent number
10741456
Date of patent
August 11, 2020
Patent application number
16156391
Date Filed
October 10, 2018
Patent citations
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US Patent 10263100 Buffer regions for blocking unwanted diffusion in nanosheet transistors
Patent primary examiner
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Grant S Withers

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