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US Patent 10553604 Through array contact structure of three-dimensional memory device

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Contents

Is a
Patent
Patent

Patent attributes

Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10553604
Patent Inventor Names
Zhenyu Lu0
Guanping Wu0
Wenguang Shi0
Xianjin Wan0
Baoyou Chen0
Date of Patent
February 4, 2020
Patent Application Number
16046843
Date Filed
July 26, 2018
Patent Citations
‌
US Patent 10074664 Semiconductor memory device including slimming structure
Patent Citations Received
‌
US Patent 12133385 Bottom select gate contacts for center staircase structures in three-dimensional memory devices
0
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US Patent 11587796 3D-NAND memory cell structure
0
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US Patent 11638377 Self-aligned select gate cut for 3D NAND
0
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US Patent 11631692 Semiconductor memory device
0
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US Patent 11785776 Through array contact structure of three-dimensional memory device
‌
US Patent 11930637 Confined charge trap layer
0
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US Patent 12022659 Three-dimensional memory device and method
0
‌
US Patent 12087621 Air gaps in memory array structures
0
...
Patent Primary Examiner
‌
Calvin Y Choi
Patent abstract

Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.

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