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US Patent 10510622 Vertically stacked complementary-FET device with independent gate control

OverviewStructured DataIssuesContributorsActivity
Is a
Patent
Patent
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Date Filed
July 27, 2018
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Date of Patent
December 17, 2019
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Patent Application Number
16047456
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Patent Citations Received
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US Patent 12136656 Semiconductor structure having two-dimensional channel
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US Patent 11315938 Stacked nanosheet rom
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US Patent 11894436 Gate-all-around monolithic stacked field effect transistors having multiple threshold voltages
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US Patent 11895818 Stacked FET SRAM
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US Patent 12080709 Dual inner spacer epitaxy in monolithic stacked FETs
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US Patent 12080714 Buried local interconnect between complementary field-effect transistor cells
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US Patent 11515334 Stacked vertically isolated MOSFET structure and method of forming the same
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US Patent 10748935 Stacked vertically isolated MOSFET structure and method of forming the same
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US Patent 11756837 Hybrid nanosheet tunnel-FET/CMOS technology
Patent Inventor Names
Julien Frougier
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Puneet Harischandra Suvarna
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Ruilong Xie
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Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
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Patent Number
10510622
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Patent Primary Examiner
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Dale E Page
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