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US Patent 10496326 Hardware double buffering using a special purpose computational unit

Patent 10496326 was granted and assigned to Google on December, 2019 by the United States Patent and Trademark Office.

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Patent abstractTimelineTable: Further ResourcesReferences
Is a
Patent
Patent

Patent attributes

Patent Applicant
Google
Google
Current Assignee
Google
Google
Patent Jurisdiction
United States Patent and Trademark Office
United States Patent and Trademark Office
Patent Number
10496326
Patent Inventor Names
Ravi Narayanaswami9
Olivier Temam9
Dong Hyuk Woo9
Harshit Khaitan9
Date of Patent
December 3, 2019
Patent Application Number
16240459
Date Filed
January 4, 2019
Patent Citations Received
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US Patent 12079711 Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies
1
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US Patent 10936942 Apparatus and mechanism for processing neural network tasks using a single chip package with multiple identical dies
2
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US Patent 11704562 Architecture for virtual instructions
3
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US Patent 11709783 Tensor data distribution using grid direct-memory access (DMA) controller
4
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US Patent 11922306 Tensor controller architecture
5
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US Patent 11954580 Spatial tiling of compute arrays with shared control
6
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US Patent 11972349 Flexible compute array utilization in a tensor processor
7
‌
US Patent 12001893 Distributed synchronization scheme
8
Patent Primary Examiner
‌
Ann J Lo
Patent abstract

Methods, systems, and apparatus, including an apparatus for transferring data using multiple buffers, including multiple memories and one or more processing units configured to determine buffer memory addresses for a sequence of data elements stored in a first data storage location that are being transferred to a second data storage location. For each group of one or more of the data elements in the sequence, a value of a buffer assignment element that can be switched between multiple values each corresponding to a different one of the memories is identified. A buffer memory address for the group of one or more data elements is determined based on the value of the buffer assignment element. The value of the buffer assignment element is switched prior to determining the buffer memory address for a subsequent group of one or more data elements of the sequence of data elements.

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