US Patent 10452480 Memory device with dynamic processing level calibration

A memory device includes a memory array including a plurality of memory cells; and a controller coupled to the memory array, the controller configured to iteratively: determine a first error rate corresponding to a current processing level for processing data corresponding to a subset of the plurality of memory cells, determine a second error rate using an offset processing level for processing the data corresponding to the subset of the plurality of memory cells, wherein the offset processing level is offset from the current processing level by a first offset amount, and generate an updated processing level for the subset of the plurality of memory cells based on a comparison of the first error rate and the second error rate.